The successful resolution of conditional branches is an important issue in modern microprocessors. When a conditional branch enters an execution pipeline, the instructions following the branch may typically wait for the branch resolution. A common solution to this problem is speculative execution: the branch outcome and/or its target may be dynamically or statically predicted, so the execution may proceed without stalling. However, if a branch is mispredicted, speculatively executed instructions are typically flushed and their results discarded, thus wasting a significant number of processor clock cycles.